This invention relates to modeling registers for electronic circuit verification. More particularly, this invention relates to a method of modeling a register at register transfer level (RTL).
The electronics industry's increasing need for very large and complex systems has put a strain on conventional design verification methodologies. By raising the level of design capture from schematic level to register transfer level (RTL), engineers can more quickly verify and debug larger and more complex systems.
However, modeling a register in RTL introduces problems that do not exist when modeling the register at a schematic level using for example Fusion HDL. Registers provide an important fundamental building block for digital systems. In some applications, registers provide a temporary storage function. In other applications registers provide a way to synchronize data signals with timing signals to form a highly accurate timing generator. Thus, accurate modeling of registers is critical for a wide variety of applications.
FIG. 1 shows a schematic symbol for a conventional D type register 100. Register 100 includes an input signal D, an output signal Q, and a clock signal CLK. The D type register 100 further includes the ability to have its output Q preset with a predetermined condition upon reset using a clear nCLR line.
FIG. 2 shows an operational waveform for illustrating the operation of a register. The nCLR signal is used to reset the register to a zero value or some predetermined value, CLK is the input clock signal, D is the input data signal and Q is the output data signal.
A D register receives an input signal D which is transferred to its output as a function of a clock signal CLK applied to it. The output value Q of the register only changes value when the clock signal CLK changes to a digital high signal. In this case, the value of the input signal D is transferred to become the output value Q. In all other cases, the output value Q from the D register remains unchanged. The D register can be designed to switch at either a rising edge or a falling edge of the clock signal.
In normal operation, the CLK value is either a digital low or a digital high. However, during contention or tristate, the CLK value fluctuates and is unknown. Contention is the condition when more than one driver is transmitting a signal to the register CLK and the values of the signals from the drivers are not the same (i.e. one driver is sending a digital high signal while the other is sending a digital low signal), thereby creating a conflict. Tristate condition exists when the register is not receiving a clock signal but there is still voltage on the line. During tristate or contention, the clock value is floating and can be any value, i.e. 0.2 v, 0.8 v or 1.5 v. Eventually the value settles on either a digital high or a digital low or some other known value. But, the short time that the clock value is floating introduces errors in data transmission when modeling in RTL. The present invention is directed to reducing these errors.